首页> 外国专利> HIGH DRY ETCH RATE MATERIALS FOR SEMICONDUCTOR PATTERNING APPLICATIONS

HIGH DRY ETCH RATE MATERIALS FOR SEMICONDUCTOR PATTERNING APPLICATIONS

机译:适用于半导体制图应用的高干蚀率材料

摘要

Methods and apparatuses for depositing low density spacers using atomic layer deposition for negative patterning schemes are provided herein. Methods involve one or more of: (1) exposing a substrate to a plasma for a duration less than about 300 ms in each cycle of alternating pulses of a deposition precursor and oxidizing plasma; (2) exposing the substrate to the plasma at a radio frequency power density of less than about 0.2 W/cm2; and (3) exposing the substrate to the plasma produced from a process gas having an argon to oxidant ratio of at least about 1:12.
机译:本文提供了使用用于负图案化方案的原子层沉积来沉积低密度间隔物的方法和设备。方法涉及以下一种或多种:(1)在沉积前体和氧化等离子体的交替脉冲的每个循环中,将衬底暴露于等离子体的时间小于约300ms; (2)以小于约0.2 W / cm 2 的射频功率密度将衬底暴露于等离子体中; (3)将衬底暴露于由氩气与氧化剂之比至少约为1:12的工艺气体产生的等离子体。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号