A method for reducing a memory operation time in a nonvolatile memory device (10) having a memory array (12) with a plurality of memory cells (1), envisages: performing a first execution of the memory operation on a set of memory cells (1) by applying a first biasing configuration; storing information associated to the first biasing configuration; performing a second execution, subsequent to said first execution, of the memory operation on the same set of memory cells (1) by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.
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