NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY

摘要

In a non-volatile memory system, a programming rate-based deceleration such as a bit line voltage rise is applied to the fast-programming storage elements. A multiple-phase programming operation using a forward-backward word line sequence is performed wherein the programming rate data is stored in the latches in one programming phase and is read from the latches for use in a subsequent programming phase of a given wordline . High-speed programming storage elements and low-speed programming nonvolatile storage elements can be distinguished such that the distinction is detected when a plurality of storage elements reaches a certain verification level, and based on the natural threshold voltage distribution of the storage elements Counting the number of additional program pulses that are set, and subsequently performing a read operation that separates the slow-programming storage elements from the fast-programming storage elements. The drain side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.