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System and method for memory control having address integrity protection for error-protected data words of memory transactions

机译:具有用于存储器事务的受错误保护的数据字的地址完整性保护的存储器控​​制的系统和方法

摘要

A system and method are provided to control error-protected access to a memory device having address integrity protection for data words of memory transactions. A communication port receives a command having a port address, which is adaptively converted to a memory address by an interface portion. The interface portion includes an adaptation stage carrying out a predefined adaptation response on an address propagated therethrough during a clock cycle of operation. An address protection portion configures the adaptation stage to maintain the predefined adaptation response over at least two clock cycles. Address error is detected based on comparison of output addresses respectively generated upon iterative propagation of the same input address through the adaptation stage over the clock cycles. A command control portion executes to adaptively split each command received from the interface portion, as well as the corresponding memory address according to an inline storage configuration of the memory device.
机译:提供一种系统和方法以控制对具有对存储器事务的数据字的地址完整性保护的存储器设备的错误保护访问。通信端口接收具有端口地址的命令,该命令被接口部分自适应地转换为存储器地址。接口部分包括适配级,该适配级在操作的时钟周期期间对通过其传播的地址执行预定的适配响应。地址保护部分将自适应级配置为在至少两个时钟周期内保持预定义的自适应响应。根据在时钟周期内通过适配级迭代传播同一输入地址时分别生成的输出地址的比较,检测地址错误。命令控制部分执行以根据存储设备的内联存储配置来自适应地划分从接口部分接收的每个命令以及对应的存储地址。

著录项

  • 公开/公告号US10303543B1

    专利类型

  • 公开/公告日2019-05-28

    原文格式PDF

  • 申请/专利权人 CADENCE DESIGN SYSTEMS INC.;

    申请/专利号US201715609539

  • 发明设计人 JOHN M. MACLAREN;

    申请日2017-05-31

  • 分类号G06F11;G06F11/10;H03M13/09;G06F11/30;G06F11/34;

  • 国家 US

  • 入库时间 2022-08-21 12:13:44

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