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PERFORMANCE AWARE WORD LINE UNDER-DRIVE READ ASSIST SCHEME FOR HIGH DENSITY SRAM TO ENABLE LOW VOLTAGE FUNCTIONALITY
PERFORMANCE AWARE WORD LINE UNDER-DRIVE READ ASSIST SCHEME FOR HIGH DENSITY SRAM TO ENABLE LOW VOLTAGE FUNCTIONALITY
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机译:用于高密度SRAM的驱动器读取辅助方案下的性能字线启用低电压功能
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摘要
PMOS-based temperature compensated read-assist circuits for low-Vmin 6T SRAM bitcells realized in nanometer scale (e.g., 7 nm) CMOS FinFET technologies generate maximum wordline lowering (lower wordline voltages) at higher temperatures and minimum wordline lowering (higher wordline voltages) at lower operating temperatures in way that is substantially process independent and avoids post-silicon tuning. A read-assist PMOS transistor is connected between an associated wordline and VSS and controlled by a temperature compensation signal produced at an intermediate node between weak pull-up and strong pull-down PMOS transistors that are connected in series between VDD and VSS and respectively controlled by VDD and VSS during read operations. This configuration generates the temperature compensation signal at a level closer to VSS at high temperatures than at low temperatures, whereby write-ability is not impacted by the read-assist circuit at low temperature. An optional actuation circuit disables the temperature compensation circuit during non-active cycles to prevent current leakage.
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