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Junctionless nanowire transistor and manufacturing method for the same

机译:无结纳米线晶体管及其制造方法

摘要

A junctionless nanowire transistor and a manufacturing method for the same are disclosed. Two terminals of each of the channel nanowires disposed in the transistor are respectively connected with the source region and the drain region; the source region, the drain region and the channel nanowires uses a same doping material such that the on-state current of the transistor is increased, and the uniformity of the transistor is increased. Besides, the multiple channel nanowires are disposed above the active layer in a stacked arrangement to increase the integration of the transistor.
机译:公开了一种无结纳米线晶体管及其制造方法。设置在晶体管中的每个沟道纳米线的两个端子分别与源极区和漏极区连接;源区,漏区和沟道纳米线使用相同的掺杂材料,从而增加了晶体管的导通电流,并且增加了晶体管的均匀性。此外,多通道纳米线以堆叠布置设置在有源层上方以增加晶体管的集成度。

著录项

  • 公开/公告号US10192954B2

    专利类型

  • 公开/公告日2019-01-29

    原文格式PDF

  • 申请/专利号US201615314057

  • 发明设计人 BO LIANG;JUN LI;WEI WANG;

    申请日2016-11-16

  • 分类号H01L29/06;H01L29/10;H01L21/308;H01L29/786;H01L29/08;H01L29/423;H01L21/3065;H01L29/417;H01L21/762;H01L29/66;B82Y10;H01L29/775;H01L21/02;H01L21/324;H01L21/3105;

  • 国家 US

  • 入库时间 2022-08-21 12:09:58

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