On-chip power supply noise reduction or reduction using a local detection loop in the processor core

摘要

PROBLEM TO BE SOLVED: To provide a technique for promoting reduction and / or reduction of on-chip power supply noise voltage by using a local detection loop in a processor core. In one example, a computer implementation method may include detecting a voltage droop in a first area of the processor core by a processor core. The computer implementation method can also include transmitting voltage droop information by the processor core to a local control located in the first area and a global control located in the processor core. Further, the computer implementation method can include applying a first mitigation measure by the processor core in a first area of the processor core in response to a local instruction received from a local control. The local instruction can include a first mitigation measure indicator. [Selection diagram] FIG. 9