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On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core
On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core
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机译:在处理器核心中使用本地检测环路的片上供电噪声降低或缓解
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摘要
Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.
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