Vertical transport fin field effect transistor and method of forming vertical transport fin field effect transistor

摘要

A method of lower dielectric isolation for a vertical transport fin field effect transistor is provided. A vertical transport fin field effect transistor (VT FinFET) includes one or more vertical fins on a surface of a substrate and an L on a substrate adjacent to at least one of the one or more vertical fins. A U-shaped or U-shaped spacer groove and a gate dielectric layer on at least one side wall of the one or more vertical fins and the L-shaped or U-shaped spacer groove. [Selection] Fig. 25