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METHOD AND GATE RUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS

机译:晶体管阈值电压调制的方法和门结构

摘要

The present technology provides a structure capable of independently adjusting the threshold voltages of an N-channel transistor and a P-channel transistor, and a manufacturing method thereof. The semiconductor device manufacturing method according to the present technology provides a method of preparing a substrate including a PMOS region and an NMOS region. step; Forming a germanium containing channel region in a substrate of the PMOS region; Forming a high dielectric layer on the substrate; Forming a threshold voltage control layer including a lanthanum-based element on the high dielectric layer of the NMOS region; Forming a first titanium nitride on the threshold voltage control layer and the high dielectric layer of the PMOS region; Forming an oxide suppression layer containing silicon on the first titanium nitride in the NMOS region; Forming a second titanium nitride on the oxide suppression layer and the first titanium nitride of the PMOS region; Forming a first gate stack including the high dielectric layer, first titanium nitride, and second titanium nitride on a substrate of the PMOS region; And forming a second gate stack including the high dielectric layer, the threshold voltage regulating layer, the first titanium nitride, and an oxide suppression layer on the substrate of the NMOS region.
机译:本技术提供了能够独立地调节N沟道晶体管和P沟道晶体管的阈值电压的结构及其制造方法。根据本技术的半导体器件制造方法提供一种制备包括PMOS区域和NMOS区域的基板的方法。步;在PMOS区域的衬底中形成含锗的沟道区域;在基板上形成高介电层;在NMOS区域的高介电层上形成包括基于镧的元素的阈值电压控制层;在PMOS区域的阈值电压控制层和高介电层上形成第一氮化钛;在NMOS区域中的第一氮化钛上形成包含硅的氧化物抑制层;在氧化物抑制层和PMOS区域的第一氮化钛上形成第二氮化钛;在PMOS区域的衬底上形成包括高介电层,第一氮化钛和第二氮化钛的第一栅极堆叠;并且在NMOS区域的衬底上形成包括高介电层,阈值电压调节层,第一氮化钛和氧化物抑制层的第二栅极堆叠。

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