Decoding separate read and write addresses in the memory system to support simultaneous memory read and write operations

摘要

Memory systems are disclosed that provide separate read and write address decoding to support simultaneous memory read and write operations. Separating read and write address decoding can avoid circuit conflicts for simultaneous memory read and write operations even when using single port memory bit cells. The read and write addresses of each read and write operation are decoded separately into read and write row and column selections driven by the memory array, so that simultaneous read and write operations are not affected by each other. To avoid circuit conflicts for simultaneous read and write operations, the memory system is configured to prioritize write row selection over read row selection to drive a row of memory bit cells in the memory array. In this way, the write operation will always be successful regardless of whether read and write row selection is for the same row.