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Wideband RF beamforming: architectures, time-delays and cmos implementations

机译:宽带RF波束成形:架构,时延和cmos实现

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摘要

A phased array antenna is a kind of antenna which is electronically reconfigurable to realize different antenna beam patterns. Delay blocks are an essential part of phased array antenna systems. Their delay-range, noise, nonlinearity, bandwidth, size, cost and power consumption have a dominant effect on the phased array antenna systems. This thesis targets CMOS implementation of delay cells suitable for compact IC implementations in standard CMOS processes, in the hundreds of MHz to low GHz range. A criterion f↑=0 has been introduced to quantify the delay vs. frequency variations in delay blocks. Mathematical formulas have been found that use f↑=0 of the delay blocks to quantify the beam direction variations in the phased array. As an approximate implementation of delay blocks, the existing gm-(R)C 1st order all-pass filters have been studied and a comparison method has been introduced to compare and benchmark them. Their circuit topologies shows that they are not directly cascade-able and have large parasitic capacitors which limit their bandwidth and are therefore unsuitable for working up to 3GHz. This has led us to the idea of a new topology for the 1st order all-pass filters. The new topology has much less parasitic components compared to other 1st order all-pass topologies, therefore it has a bandwidth up to 5x more compared to the aforementioned 1st order gm-(R)C filters. In order to demonstrate the functionality of the delay block, it has been designed and used in implementation of a 4 antenna element phased array antenna chip at 160nm technology and measurements results showed its bandwidth is wide enough to cover frequencies from 1GHz to 2.5GHz. Measurement results proved that the 1st order gm-C filters are suitable for the realization of the wideband phased array antenna system.
机译:相控阵天线是一种天线,可以通过电子方式重新配置以实现不同的天线波束方向图。延迟块是相控阵天线系统的重要组成部分。它们的延迟范围,噪声,非线性,带宽,尺寸,成本和功耗对相控阵天线系统起主要作用。本论文的目标是在数百MHz至低GHz范围内适合于标准CMOS工艺中紧凑型IC实现的延迟单元的CMOS实现。已经引入了标准f 1 = 0,以量化延迟块中的延迟与频率变化。已经发现了使用延迟块的f 1 = 0来量化相控阵中的光束方向变化的数学公式。作为延迟块的近似实现,对现有的gm-(R)C一阶全通滤波器进行了研究,并引入了比较方法对它们进行比较和基准测试。它们的电路拓扑表明它们不能直接级联,并且具有大型寄生电容器,这限制了它们的带宽,因此不适合在高达3GHz的频率下工作。这使我们想到了针对一阶全通滤波器的新拓扑的想法。与其他一阶全通拓扑相比,新拓扑具有更少的寄生成分,因此与前述的一阶gm-(C)滤波器相比,其带宽高达5倍。为了演示延迟模块的功能,已设计并在160nm技术下实现了4天线元件相控阵天线芯片的实现,测量结果表明其带宽足够宽,可以覆盖1GHz至2.5GHz的频率。测量结果证明,一阶gm-C滤波器适用于宽带相控阵天线系统的实现。

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    Garakoui, S.K.;

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  • 年度 2015
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