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Hardware Trojan Detection in Third Party Digital IP Cores

机译:第三方数字IP内核中的硬件木马检测

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摘要

Due to Globalization outsourcing of SoC designs either for verification, testing and fabrication has become inevitable. Modern System on chip (SoC) is complex process. Modern SoC‟s can be designed time effectively and cost effectively with the help of third party Intellectual Property (IP) core vendors. Various processors cores (like ARM, Power PC), communication controllers (CAN, Zigbee) and control cores (PWM, Analog comparator) will get incorporated into SoC‟s, which are supplied by different vendors. The original SoC manufacturers are IP integrators, targeting a particular application. In this process, various issues like IP protection, IP rights and problem of malicious IP‟s will arise. Recent addition in this list is Hardware Trojans (HT). HT‟s can be included by rogue designer in design house or at overseas fabrication factories. The objective of these HT‟s includes manipulating the functionality of the chip, leaking confidential information and destroying the system. HT‟s included in the design phase must be weeded out during verification phase. Still now, there is no concrete method or golden rule in the existing verification framework to detect the HT‟s. Various verification metrics like code coverage, functional coverage and verification methodologies like OVM or UVM will be helpful in detecting HT‟s. Formal verification is also useful. A comprehensive framework using all verification metrics is very much required to detect HT‟s. We will address this issue in our thesis. Secondly, static timing analysis (STA) and power analysis (PA) can be used to detect HT‟s included at both design phase and also in fabrication. In our proposed framework, we will incorporate verification metrics, formal verification, STA and PA to detect HT‟s. In this report, we apply DFT techniques and standard verification metrics to detect the hardware Trojans. The microprocessors and cryptographic designs are most vulnerable for hardware Trojan attacks. The Advanced Encryption Standard (AES) and RSA Trojan benchmarks from Trust Hub are used to verify the existing test principles like stuck at fault (SAF), path delay faults (PDF) are capable of detecting Trojans in Benchmarks. Results and analysis is presented in this report. Also Novel Trojan Benchmarks designs were proposed to eliminate the existing weaknesses in AES Benchmarks.
机译:由于全球化,用于验证,测试和制造的SoC设计外包已成为必然。现代片上系统(SoC)是一个复杂的过程。借助第三方知识产权(IP)核心供应商,可以有效地设计时间和成本效益的现代SoC。各种处理器内核(例如ARM,Power PC),通信控制器(CAN,Zigbee)和控制内核(PWM,模拟比较器)将被合并到SoC中,这是由不同供应商提供的。最初的SoC制造商是针对特定应用的IP集成商。在此过程中,会出现各种问题,例如IP保护,IP权利和恶意IP问题。此列表中最近添加的是硬件木马(HT)。流氓设计师可以将HT包括在设计公司或海外制造工厂中。这些HT的目标包括操纵芯片的功能,泄露机密信息并破坏系统。设计阶段中包含的HT必须在验证阶段中清除。到目前为止,现有的验证框架中还没有检测HT的具体方法或黄金法则。各种验证指标(如代码覆盖率,功能覆盖率和验证方法,如OVM或UVM)将有助于检测HT。形式验证也很有用。要检测HT,非常需要使用所有验证指标的综合框架。我们将在论文中解决这个问题。其次,静态时序分析(STA)和功率分析(PA)可用于检测在设计阶段和制造过程中都包含的HT。在我们提出的框架中,我们将合并验证指标,正式验证,STA和PA以检测HT。在此报告中,我们应用DFT技术和标准验证指标来检测硬件木马。微处理器和密码设计最容易受到硬件Trojan攻击。 Trust Hub的高级加密标准(AES)和RSA Trojan基准用于验证现有的测试原理,例如卡在故障(SAF),路径延迟故障(PDF)能够检测基准中的木马。结果和分析在本报告中介绍。还提出了新颖的Trojan基准测试设计,以消除AES基准测试中的现有弱点。

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    Chanamala Rakesh;

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  • 年度 2015
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