A hierarchical modeling and virtual prototyping methodology for functional verification of RF mixed-signal SoCs

摘要

The commercial success of wireless SoCs including RF subsystems has led to fast-growing demand for efficient functional verification. Recent developments have increase simulation efficiency of RF subsystems by eliminating the need for solving large sets of differential equations at high speed. Modeling accuracy hasto be traded against verification coverage to keep up with the increasing design complexity of SoC applications. In this work is a functional verification methodology that is suited for the modern SoC systems including analog/RF subsystems prior to tapeout is developed. First, an overview of different verification methods, modeling languages, and approaches, including their advantages and disadvantages has to be provided. Based on the investigation the most suitable method is defined. It should consist of efficient modeling methods that enable fast simulation at different levels of design hierarchy and different phases of the design process. In addition to being fast, methods maintaining the consistency between models and circuits, including the pin-compatibility and design parameter parity, also have to be given. Once the flow is defined, automation concepts will also be worked out. An automated hierarchical SystemC virtual RF prototyping method targeting model creation that is based on the circuit design database will also be implemented, which seamlessly links the system level and block/circuit level design by generating a pin accurate, specification oriented virtual prototype with high simulation performance. Finally, the feasibility of the proposed modeling and verification methodology has to be exemplified by the results of industry-oriented projects.