A novel approach for generating digital chirp signals using FPGA technology for synthetic aperture radar applications

摘要

In this dissertation a novel digital chirp signal generator is proposed, analyzed, and realized. The new system generates digital chirp signals with the lowest level of spurious harmonic distortion, less memory size and low hardware complexity in comparison with other systems and techniques reported in the literature. In this improved digital chirp generator the start frequency and phase can be controlled by the initial content of the counter and the accumulator. Furthermore, the sweep rate can also be controlled by means of location and size of the address lines. The proposed system is a hybrid of the digital chirp generator and the system using the methodology of the piecewise polynomial interpolation based on the direct digital frequency synthesizer. Moreover, an optimization technique is applied to enhance the performance of this chirp generator and to avoid the attenuation in the speed of its operations.The new digital chirp generator uses a clock to trigger the counter (first integrator) and after that its output feeds the accumulator (second integrator), the decimal value of selected digital lines of the content of the accumulator, which represents the phase, is then used to calculate the value of the chirp sine using the interpolator. This interpolator uses predetermined interpolation coefficients to fit the sine wave from the calculated phase instead of using a predetermined waveform stored in a big size memory. This implies, that a smaller look-up table for sine and cosine functions is used in comparison with the previous techniques.A new improved parallel processing technique is proposed in order to increase the bandwidth of the chirp signal up to 320 MHz and more based on the used level of the parallelism. As a comparison with the look-up table method, the size of the ROM in the new method is reduced by a factor of more than 128 when using 12 address lines, and Spurious Free Dynamic Range (SFDR) reaching 100.9 dBc.The system is realized using the Innovation Integration X5-TX platform with FPGA Xilinx VIRTEX-5 used with the parallel processing technique to generate a chirp signal with high bandwidth up to 320MHz using 200 MHz clock frequency.