Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia

摘要

Three main analog circuit building blocks that are important for a mixed-signalsystem are investigated in this work. New building blocks with emphasis on powerefficiency and compatibility with deep-submicron technology are proposed andexperimental results from prototype integrated circuits are presented.Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer thatcontrols inter-symbol interference and provides anti-alias filtering for the subsequentanalog to digital converter is presented. The equalizer design is based on a new seriesLC resonator biquad whose power efficiency is analytically shown to be better than aconventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18?mCMOS technology. It is experimentally verified to achieve an equalization gainprogrammable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mWof power. This corresponds to more than 7 times improvement in power efficiency overconventional Gm-C equalizers.Secondly, a load capacitance aware compensation for 3-stage amplifiers ispresented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load whileconsuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS powerof 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a smallarea of 0.1mm2. The power consumption is reduced by about 10 times compared todrivers that can support such a wide range of capacitive loads.Thirdly, a novel approach to design of ADC in deep-submicron technology isdescribed. The presented technique enables the usage of time-to-digital converter (TDC)in a delta-sigma modulator in a manner that takes advantage of its high timing precisionwhile noise-shaping the error due to its limited time resolution. A prototype ADCdesigned based on this deep-submicron technology friendly architecture was fabricatedin a 65nm digital CMOS technology. The ADC is experimentally shown to achieve68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. Itis projected to reduce power and improve speed with technology scaling.