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Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems

机译:基于网络的芯片芯片多处理器系统的模糊流量调节

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摘要

As large uniprocessors are no longer scaling in performance, chip multiprocessors (CMP) become the mainstream to build high-performance computers. CMP chips integrate various components such as processing cores, L1 caches and L2 caches (some also contain L3 caches, for example, in the IBM Power7 multicore processor) together, and multiple CMP chips with external memory banks make up a CMP system. As buses (although long the mainstay of system interconnect) are unable to keep up with increasing performance requirements, network-on-chip (NoC) offers an attractive solution to this communication crisis and is becoming the pervasive interconnection network in CMPs. In NoC based CMP systems, regulating traffic flows has been shown to be an effective means to improve communication performance and reduce buffer requirements. However, existing flow regulation policies such as the ones describe in [8] and [9] are all static. The parameters (δ,ρ) of the regulators are hard-coded during system configuration, where δ bounds the traffic burst and ρ the traffic rate. Although static flow regulator can be used as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, the drawbacks from its static property cancel the gains in some situations. In this thesis, we design a fuzzy flow regulation mechanism for network-onchip based CMPs. Being different from static flow regulation policy, our system makes regulation decisions dynamically according to the state of interconnection network. We use fuzzy logic to mimic the behaviors of an expert that validly controls the admission of input flows, with the aim of making better use of on-chip resources and decreasing communication delays. We implement and test our design under Multi-facet’s General Executiondriven Multiprocessor Simulator (GEMS), which creates a platform that is similar to real CMP environment. Hardware imitating models such as L1 caches, L2 caches and memory banks help us to test our design thoroughly and comprehensively. The experiments are done with both closed-loop and open-loop methods. Comparisons have been made between our design and static regulation policy. The results show that our fuzzy flow regulation system can make good regulation policy with all the testing cases.
机译:由于大单处理器不再在性能提升,芯片多(CMP)成为主流打造的高性能计算机。 CMP芯片整合各种部件,诸如处理核,L1高速缓存和L2高速缓存(有的还含有L3高速缓存,例如,在IBM的Power7多核处理器)一起,并且多个CMP芯片与外部存储体构成一个CMP系统。由于公交车(虽然系统互连的长支柱)都无法跟上增长的性能需求,网络级芯片(NOC)提供了一个有吸引力的解决方案,这种沟通危机,正成为中医的普遍互连网络。在基于NoC的CMP系统中,调节流量流已被证明是改善通信性能,并减少缓冲器的要求的有效手段。然而,现有的流量调节策略如那些在[8]和[9]描述都是静态的。调节器的参数(δ,ρ)是硬编码的过程中的系统配置,其中,δ界定的业务脉冲串和ρ流量速率。虽然静态流量调节器可以被用作设计仪器系统级芯片(SoC)的建筑师控制质量的服务,实现成本有效的通信,从它的静态特性的缺点取消在某些情况下的增益。在本文中,我们设计了网络的片上基于中医模糊流量调节机制。作为从静流调控政策不同,我们的系统会动态地根据互连网络的国家调控决策。我们使用模糊逻辑来模仿有效地控制输入的接纳流动,以更好地利用片上资源的和减少通信延迟的目的专家的行为。我们实施和测试我们在多面的总Executiondriven多处理器模拟器(GEMS),它创建了一个平台,类似于真正的CMP环境设计。硬件模仿车型如L1高速缓存,L2高速缓存和内存的银行帮助我们彻底和全面的测试我们的设计。该实验既闭环和开环方式进行。比较已经使我们的设计和静态监管政策之间。结果表明,我们的模糊流量调节系统,可以很好地调控政策与所有的测试用例。

著录项

  • 作者

    Yuan Yao; Zhonghai Lu;

  • 作者单位
  • 年度 2014
  • 总页数
  • 原文格式 PDF
  • 正文语种 eng
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