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High injection and carrier pile-up in lattice matched InGaAs/InP PN diodes for thermophotovoltaic applications

机译:晶格匹配的InGaAs / InP PN二极管中的高注入和载流子堆积,适用于热光电应用

摘要

This article analyzes and explains the observed temperature dependence of the forward dark current of lattice matched In0.53Ga0.47As on InP diodes as a function of voltage. The experimental results show, at high temperatures, the characteristic current-voltage (I-V) curve corresponding to leakage, recombination, and diffusion currents, but at low temperatures an additional region is seen at high fields. We show that the onset of this region commences with high injection into the lower-doped base region. The high injection is shown by using simulation software to substantially alter the minority carrier concentration profile in the base, emitter and consequently the quasi-Fermi levels (QFL) at the base/window and the window/cap heterojunctions. We show that this QFL splitting and the associated electron "pile-up" (accumulation) at the window/emitter heterojunction leads to the observed pseudo-n=2 region of the current-voltage curve. We confirm this phenomenon by investigating the I-V-T characteristics of diodes with an InGaAsP quaternary layer (E-g=1 eV) inserted between the InP window (E-g=1.35 eV) and the InGaAs emitter (E-g=0.72 eV) where it serves to reduce the barrier to injected electrons, thereby reducing the "pile-up." We show, in this case that the high injection occurs at a higher voltage and lower temperature than for the ternary device, thereby confirming the role of the "accumulation" in the change of the I-V characteristics from n=1 to pseudo-n=2 in the ternary latticed matched device. This is an important phenomenon for consideration in thermophotovoltaic applications. We, also show that the activation energy at medium and high voltages corresponds to the InP/InGaAs conduction band offset at the window/emitter heterointerface.
机译:本文分析并解释了InP二极管上晶格匹配的In0.53Ga0.47As的正向暗电流与电压之间的函数关系。实验结果表明,在高温下,对应于泄漏,复合和扩散电流的特征电流-电压(I-V)曲线,但在低温下,在高电场下会看到一个附加区域。我们表明,该区域的发病始于向低掺杂基区的高注入。通过使用仿真软件可以显着改变基极,发射极中少数载流子浓度曲线,从而改变基极/窗口和窗口/盖异质结处的准费米能级(QFL),从而实现高注入。我们表明,在窗口/发射极异质结处,这种QFL分裂和相关的电子“堆积”(积累)导致了电流-电压曲线的伪n = 2区域。我们通过研究在InP窗口(Eg = 1.35 eV)和InGaAs发射极(Eg = 0.72 eV)之间插入InGaAsP四元层(Eg = 1 eV)的二极管的IVT特性来确认这种现象,该二极管用于减小势垒注入电子,从而减少“堆积”。我们表明,在这种情况下,高注入发生在比三元器件更高的电压和更低的温度下,从而证实了“累积”在IV特性从n = 1到伪n = 2的变化中的作用。在三元格子匹配设备中。这是在热电应用中需要考虑的重要现象。我们还表明,在中压和高压下的活化能对应于窗口/发射极异质界面处的InP / InGaAs导带偏移。

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