FIFO Buffer with Real-Time Interface

摘要

The design of a FIFO buffer with fully asynchronous, non-blocking write and read211u001eoperation is presented. The buffer's logic consists of a standard self-timed FIFO 211u001e(e.g. pipeline) surrounded by two special interface blocks, In and Out, connected 211u001eto Writer and Reader, respectively. To avoid temporal blocking of Writer 211u001erequesting for a write when the pipeline is full the In block implements skipping 211u001eof the data item. Similarly, if Reader attempts to read an empty pipe, to avoid 211u001eits blocking, a special acknowledge signal is produced telling Reader to re-read 211u001ethe previous item. These blocks are synthesized from their Signal Transition 211u001eGraph (STG) specifications using an asynchronous circuit synthesis tool, petrify. 211u001eThe proposed solution is compared and contrasted against a previously known four-211u001eslot mechanism.