Arithmetic Unit of Illiac III: Simulation and Logical Design

摘要

The arithmetic unit (AU) is being simulated at the hardware level of detail. The simulation is written in PL/1 for the IBM 360/75 computer. It also serves as a dynamic documentation for the logical design of AU. The AU registers may be simulated either as structure, array or bit string. In the AU, most Boolean operations concerned with any register involves every bit of the register. In this case, bit-string operation is the most suitable operation and less time consuming. Since this simulation program is also to serve as dynamic documentation, it requires a simple, easily understood program which is very close to the actual logical design. The bit-string operation is a very straight forward operation; array or structure operations don't have any particular advantage in this simulation. All registers and indicators are simulated as bit strings; all counters are simulated as fixed point number; all gating functions are simulated as procedures and grouped into one subprogram. The Sign-Digit Subtractor (SDS) and propagation logic are simulated as two subprograms. Every arithmetic order is simulated as one subprogram (including functional sub-blocks, such as quotient selector, multiplier recoder, etc.). This simulator, therefore, is composed of one main program and several subprograms. (Author)