Comparison of Input/Output Structures for Single Chip VLSI Systolic Arrays

摘要

Operand I/O for VLSI systolic array computing structures fundamentally suffers from a potential bottleneck problem due to practical fabrication limitations of pin-outs and packaging considerations. A MUX/DMUX or similar circuit structure is necessary to convert the essentially serial global communication channels to a highly parallel internal communication scheme. These front-end additions can potentially degrade throughput and cause undue idle time in the internal high speed architecture. Three I/O circuit design candidates are presented and evaluated. Using a circuit simulation model comparisons are made as to minimum chip real estate requirements and propagation delays. Best designs are chosen. It is shown that, for reasonable operand and problem sizes, I/O bottlenecking does not occur using the chosen design.