Floor Planning and Net Assignment in Layout Compilation

摘要

The layout design of a silicon compiler is reviewed. The environment in terms of input, output and data bases is discussed. A complete design process is outlined and interpretated as an application of the principles of stepwise refinement to the design of complex integrated circuits. The rationale behind the chosen system decomposition, accepted restraints, and methods for cell assembling is emphasized. An annealing algorithm is summarized. The use of the algorithm for floor plan design, used state spaces and moves, and the way the score function is computed are described. An automatic control schedule is described. A method for the global wiring of custom layout of ICs is given.