SEU (Single-Event-Upset) Characterization of a Hardened CMOS 64K and 256K SRAM.

摘要

The first single-event-upset (SEU) tests of the AT&T 64K and 256K SRAMs have been performed. Feedback resistor values for these parts ranged from 200k(Omega) to 1M(Omega). All were fabricated using the 1-(mu)m 2-level poly, 2-level metal process. Ions used for these tests were Ar, Cu, Kr, and Xe providing a range of effective LET values from 20 to 129 MeV-cm(sup 2)/mg. With the 64K SRAM operating at 4.5 volts and 90(degree)C, an upset threshold LET of 30 MeV-cm(sup 2)/mg and saturation cross-section of 1.5 (times) 10(sup (minus)2) cm(sup 2) were measured with a nominal room temperature feedback resistance of 450k(Omega). In Adam's 10% worst-case environment using the Petersen approximation, this implies an error rate of 1.3 (times) 10(sup (minus)7) errors per bit-day. With a nominal 650k(Omega) feedback resistance, a 256K SRAM had a calculated error rate of about 3 (times) 10(sup (minus)8) errors per bit-day at 4.5 volts and 90(degree)C. This data agrees well with earlier data for a 1K-bit test chip. The minimal feedback resistance required to prevent upset vs LET is calculated by assuming an activation energy of 0.10 eV to estimate the decrease in feedback resistor value as a function of temperature. 22 refs., 8 figs., 1 tab.