Technological Development for Interfacing Parallel Access Memories to Parallel Computers

摘要

During this AASERT program, we have carried out the fabrication and evaluation of high speed receiver circuits implemented with this technology. To demonstrate the providing a bandwidth of 9GHz and an 8x8 III-V active-pixel sensor array with 285 MHz operation, In this report, we present a complete characterization of this smart pixel technology, including the S- and Y- parameters extraction for the typical devices implemented by this technology.