Software Fault Tolerance for Parallel Signal Processors

摘要

Military combat weapon systems are becoming increasingly reliant on advanced multiprocessor computer architectures to execute powerful real-time signal processing algorithms. These multiprocessor computer architectures must meet stringent system reliability, availability, and maintainability requirements. This paper addresses software-based fault tolerance techniques that can leverage inherent capabilities of multiprocessor computers to minimize overall system hardware redundancy requirements and provide quick, flexible fault detection, isolation, and recovery. An AEGIS SPY radar signal processing system example is used to illustrate fault tolerance approaches being jointly developed by MIT Lincoln Laboratory and Lockheed Martin Naval Electronic and Surface Surveillance.