Algorithms for Data Intensive Applications on Intelligent and Smart Memories.

摘要

The objective of this project was to develop an algorithmic framework that enables effective and efficient mapping of data intensive applications onto Intelligent and Smart memory architectures, as well as traditional cache architectures. Intelligent memories integrate processing logic on the same chip as memory and support high bandwidth and low latency memory access to on-chip memory. Smart memory architectures provide the ability to adapt the hardware behavior by modifying the memory controllers to enhance cache and memory performance. Effective use of these novel features requires innovative mapping techniques in addition to the utilization of higher bandwidth and/or lower latency offered by these advanced architectures. This report details the research accomplished in this project. In Section 1 we present a summary of the work accomplished, highlighting some of the results and approaches investigated. Section 2 contains copies of all papers published that acknowledge this contract. Section 3 contains the final stressmark results and analysis of the methods used to optimize various data-intensive stressmarks. Section 4 contains information about the source code, including methods for building the code, and the platforms for which the code is intended. The CD included with this binder contains all of the source code used in the project, with instructions for building the code, and a soft copy of the complete report.