Decomposition of HPEC Applications Mapped to the Natural Decomposition of a Solution Architectures -- Another Way to Think about Solving HPEC Problems

摘要

In the past, all large-scale computer architectures that were designed by so-called Digital Signal Processing (DSP) vendors were of the 'kitchen sink' approach. Each board unit incorporated all of the features that one could possibly want into a single unified design. Processors, I/O, memory, and interconnects were all available in one product, thereby increasing per slot functionality, but often at the burden of complexity, reliability, and overall cost. While this was convenient at the time, the user was required to support all of the key building blocks with solutions that were vendor unique and not always necessary for application success. An examination of high performance embedded computing (HPEC) applications shows that nearly all of them have a very distinctive and natural decomposition of the problem space such that there is a distinct I/O and data management portion and another distinct compute portion. Wrapped around both components is the need for global communications as well as system state and health management. In most instances the delivered solution was burdened with many facilities that were not of any value and that robbed the system of valuable real estate and/or reliability simplicities. This paper addresses an industry unique architectural approach to addressing the needs of HPEC applications through the use of distinctive, upgradeable, and naturally decomposed solution elements. This approach provides an application space with the freedom to address complex solutions without the burden of the kitchen sink approach. The paper's focus is on the adoption of highly flexible data acquisition servers and highly focused compute servers, each of which addresses the unique needs of real-time signal and image processing. Advances in COTS components are integral to this capability. A comparison between traditional HPEC systems and Next Generation architectures also is presented. Twelve briefing charts summarize the presentation.