Design Techniques for Radiation Hardened Phase-Locked Loops

摘要

Spacecraft experience radiation in the course of their operation and all the electronic equipment on-board these vehicles has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single-event transients (SET) in phase-locked loops -- an important circuit block for communication circuits and clock generation. The design of a digital phase-locked loop made tolerant to SET through redundancy and error correction techniques is described. Digital phase- locked loops also can incorporate self-calibration techniques to compensate for the effects of TID. A linear analysis is presented for the design of digital phase-locked loops. This digital phase-locked loop was fabricated in the Honeywell 0.35 micrometer SOI CMOS process.