Towards Trustable Embedded Systems: Hardware Threat Modeling for Integrated Circuits

摘要

As integrated circuits become more complex, it becomes easier to hide malicious logic constructs within a design. Security-conscious hardware designers require a way to detect such logic embedded in Third Party IP blocks used by their designs. The aim of this project was to develop a systematic way to detect attacks implemented in a design. Using the Java programming language, a tool capable of producing an attacker-centric threat model was developed. The tool uses a library of predefined malicious patterns to detect and categorize attacks in a system. Upon completion, the tool was tested on a small RISC microprocessor containing denial of service and data tampering attacks. Once given the appropriate library pattern, the tool was able to detect both threats in the design.