Test Generation and Fault Isolation for Microprocessors and Their Support Devices

摘要

This report covers the generation of tests for complex digital devices, implementation of those tests on currently available ATE, and fault isolation. Techniques are described for the modeling of devices in order to facilitate the testing process. A new algorithm for fault dictionary searching is given. Voltage Contrast (on the Scanning Electron Microscope) was used as an aid for fault insertion, which in turn provided test cases for fault isolation. Computer-Aided Test techniques are described. As the demonstration vehicle for this work was the development of MIL-M-38510 Detail Specifications (Slash Sheets) a tutorial description of a recommended slash sheet format is given. Many areas were only touched on during this contract; these have been described, with suggestions for further research topics. (Author)