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Design Fault Directed Test Generation for Microprocessor Validation

机译：用于微处理器验证的设计故障定向测试生成

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Deepak A. Mathaikutty; Sreekumar V. Kodakara; Eep Shukla; David Lilja;
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年度 2008
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专利

1. Design, implementation and testing of a microprocessor-based high-speed relay for detecting transformer winding faults [J] . Sidhu T.S., Sachdev M.S. IEEE Transactions on Power Delivery . 1992,第1期

机译：用于检测变压器绕组故障的基于微处理器的高速继电器的设计，实现和测试
2. Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors [J] . Lingappan L., Jha N.K. IEEE transactions on very large scale integration (VLSI) systems . 2007,第5期

机译：基于满意度的微处理器自动测试程序生成和设计
3. Developing Optimal Directed Random Testing Technique to Reduce Interactive Faults-Systematic Literature and Design Methodology [J] . K. Koteswara Rao, G. S. V. P. Raju Indian Journal of Science and Technology . 2015,第8期

机译：开发最佳定向随机测试技术以减少交互式故障-系统文献和设计方法
4. Design fault directed test generation for microprocessor validation [C] . Deepak A. Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, EDBT/ICDT Workshops . 2009

机译：设计故障定向测试生成，用于微处理器验证
5. Transition faults and transition path delay faults: Test generation, path selection, and built-in generation of functional broadside tests. [D] . Yao, Bo. 2013

机译：过渡故障和过渡路径延迟故障：测试生成，路径选择以及功能性侧面测试的内置生成。
6. Design and Experimental Validation for Direct-Drive Fault-Tolerant Permanent-Magnet Vernier Machines [O] . Guohai Liu, Junqin Yang, Ming Chen, -1

机译：直接驱动容错永磁游标机的设计与实验验证
7. Design Fault Directed Test Generation for Microprocessor Validation [O] . 2008

机译：用于微处理器验证的设计故障定向测试生成
8. Test Generation and Fault Isolation for Microprocessors and Their Support Devices [R] . Debany, W. H., O'Connor, D. A., Teague, B. K., 1980

机译：微处理器及其支持设备的测试生成和故障隔离

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