LSI (Large Scale Integrated) Design for Testability. Final Report of Design, Demonstration, and Testability Analysis

摘要

The objective of this effort was to demonstrate IBM Level Sensitive Scan Design methodology as an approach for improving the testability of military LSI/VLSI circuits. LSSD was demonstrated in an LSI component AP101C test bed to be a viable and attractive design approach for military LSI/VLSI components. (Author)