Effect of Logic Block Complexity on Area of Programmable Gate Arrays

摘要

The Programmable Gate Array (PGA) is an exciting new idea in semi-custom integrated circuits that reduces the IC manufacturing time from months to minutes and prototype cost from tens of kilo-dollars to under $100. It is similar to a gate array in structure, but can be field-programmed to specify the function of the basic logic blocks and their interconnection. This paper studies the effect of logic block complexity on total circuit area for PGAs. The architecture of a PGA consists of its logic block function, interconnection scheme, input/output block design and the global structure. There are many tradeoffs between architecture, area, and speed, each of which depends heavily on the programming technology. Programing technology is the underlying method by which the logic function is set and the connections are implemented at program time. This paper focuses on the effect of logic block complexity on PGA area, ignoring speed considerations. While circuit speed is very important, this work represents an initial exploration into plausible architectures from an area perspective. (KR)