Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications.

摘要

The design of a device that controls the sequence and timing of deployment of CubeSats on the Naval Postgraduate School's CubeSat Launcher (NPSCuL) is detailed in this thesis. This design is intended to be implemented on a fieldprogrammable gate array (FPGA) installed into the NPSCuL. This configuration allows flexibility in reprogramming the launch sequence and adding additional functionality in future designs. Operating an FPGA on orbit presents unique challenges due to the radiation environment. Radiation from space cannot be shielded efficiently, so devices must be tolerant of the expected effects. The most common effect, the single-event upset can have detrimental effects on operating electronics, causing undesired changes to data. To combat this problem, fault tolerant techniques, such as triple-modular redundancy (TMR) are explored. In these methods, multiple redundant copies of the design are operated simultaneously, and the outputs are voted on by special circuits to eliminate errors. Comparisons between manual and software generated TMR methods are tested, and the design is implemented on test hardware for further verification. Finally, future research and testing is discussed to continue to ready the design for employment of the sequencer on an actual space mission.