Design of an Implicit Pulse Triggered Flip-Flop Using PTL Based and Logic for Space Applications.

摘要

In this paper, a novel low-power pulse-triggered flip-flop (FF) design for space applications is presented. In this the clock generation circuitry an AND function is removed and is replaced with a Pass-Transistor logic based AND gate. Since in the PTL-style AND gate the n-mo s transistors are in parallel they consume less power and provides a faster discharge of the pulse resulting in miniaturization and power consumption reduction in satellites. A software package called the TANN ER EDA tools utilizing MOSIS 90nm technology is used for the study