Structure of the wafer fused InP (001)-GaAs (001) interface

摘要

A structural study of wafer fused InP-GaAs interfaces has been carried out. The geometry of the dislocation network which accommodates the twist and the lattice mismatch is first given using a geometrical approach. Cross-sectional transmission electron microscopy and plan view observations are presented. Two different misfit cases are observed. (1) When no twist is present, the 3.7% lattice mismatch is relaxed by a regular square network of dislocations with pure edge character. (2) When an additional twist is present, a square network of dislocations results as well but here the dislocations have a mixed character; 60o dislocations are also observed, some form closed defect circuits and others very likely accommodate a small tilt. The interaction between the 60o dislocations and the edge dislocations is explained in detail. Voids or inclusions are also observed as well as additional dislocations which may accommodate part of the thermal mismatch.