OPTIMIZATION OF CMOS-INTEGRATED LC OSCILLATORS USING THE GENETIC ALGORITHM

摘要

This paper reports on state-of-the-art power-frequency-normalized phase noise of 21 dB, obtained from a CMOS-integrated LC oscillator with a measured phase noise of -112 dBc/Hz at 100 kHz from the 5.3-GHz center frequency and with power consumption of 15 mW. The excellent performance of the oscillator is attributed to the careful selection of the oscillator-circuit parameters, which determined using the genetic algorithm.