Ultra thin ICs and MEMS elements: techniques for wafer thinning, stress-free separation, assembly and interconnection

摘要

Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established back-grinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the "Dicing-by-Thinning" (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting.