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Effects of base layer thickness on reliability of CVD Si{sub}3N{sub}4 stack gate dielectrics

机译:基层厚度对CVD Si{sub}3N{sub}4叠栅电介质可靠性的影响

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摘要

Effects of the base layer in Si{sub}3N{sub}4/SiON stack gate dielectrics, in particular, the physical thickness of the base layer, on the dielectric reliability, MOSFET performance and process controllability are investigated. It is found that the electrical characteristics such as TDDB lifetime as well as the Si{sub}3N{sub}4 film property in Si{sub}3N{sub}4/SiON stack dielectrics with the same capacitance oxide equivalent thickness strongly depend on the SiON-base layer thickness. From the TDDB measurements for both stress polarities and from the Si{sub}3N{sub}4 stoichiometry by the X-ray photoelectron spectroscopy analysis, the optimum SiON-base layer thickness is determined to be approximately 1 nm, in order to obtain longer TDDB lifetime and surperior n-ch MOSFET performance. The obtained results are considered to attribute to the nitrogen profile in the Si{sub}3N{sub}4/SiON stack dielectrics and the strained layer thickness near SiON/Si interface.
机译:研究了Si{sub}3N{sub}4/SiON电堆栅极电介质中基层,特别是基层的物理厚度对介电可靠性、MOSFET性能和工艺可控性的影响。结果表明,相同电容氧化物当量厚度的Si{sub}3N{sub}4/SiON电堆电介质的TDDB寿命以及Si{sub}3N{sub}4薄膜特性与SiON基层厚度密切相关。通过对应力极性的TDDB测量和X射线光电子能谱分析的Si{sub}3N{sub}4化学计量,确定最佳SiON基层厚度约为1 nm,以获得更长的TDDB寿命和超n沟道MOSFET性能。所得结果归因于Si{sub}3N{sub}4/SiON电堆电介质中的氮分布和SiON/Si界面附近的应变层厚。

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