Design of Low Leakage Power Wallace Tree Multiplier Using SVL Circuits

摘要

In this research work a Wallace tree multiplier is proposed. The Multiplier is the key block and decides the processors efficiency. The objective of this work is analysing different powers in Wallace Tree multiplier, which is implemented using 8Transistor (T), 28T Standard Complementary Metal Oxide Semiconductor (CMOS) full adder and 28T, 8T full adders with Self Controllable Voltage (SVL) circuits. As the transistor sizes are shrinking down to improve integration density and performance, the threshold voltages also being reduced [11]. With the reduction of threshold voltages leakage current is increasing more, especially when the device is in idle mode. The proposed SVL circuits supplies maximum dc voltage to the logic design (load circuit), when the device is in active mode to give normal operation and minimum dc voltage when the device is in standby mode, to reduce leakage power [1]. The proposed SVL circuits minimized power consumption compared to standard CMOS Technique with the minimal area overhead and speed degradation. Wallace tree multiplier realized using 28T full adders with SVL circuits reduced 72.3% leakage power, 8T full adders with SVL circuits minimized 34% leakage power compared to Wallace tree multiplier realized using CMOS 28T, 8T full adders respectively. All simulations done using CADENCE Tool in 180nm CMOS technology.