Design and Implementation of Low Power and Efficient Adders - A Review

摘要

In the present VLSI circuit designs, there is enormous increase in the power consumption due to the increasing speed and complexity of the circuits. It is known that the demand for portable equipment like laptops and cellular phones is increasing rapidly. Attention has been focused on power efficient circuit designs. Adders are the basic building blocks of the complex arithmetic circuits and are widely used in Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), and floating point units, for address generation in case of cache or memory access and in digital signal processing. This paper discusses various types of adders and their features. Brief description has been provided on various multipliers. Categorization of adders w.r.t delay time and capacity has been exemplified. From the review, it is noted that: (i) designers should see carefully on the accuracy of the models keeping in view of consequences; (ii) an accurate representation of how a microchip dissipates power for good design and (iii) reliable and proper circuit activity for energy dissipation.