A fast redundant binary multiplier excluding the intermediate sum operation of redundant binary adders

摘要

Accelerating methods that use a redundant binary representation for multipliers are good for VLSI implementation and have been concentrated lately. We examine an accelerating method for redundant binary multipliers using second order Booth's method. At a redundant binary multiplier which Booth's method is applied to, partial products are generated by every two digit of a multiplier and are accumulated. In this paper, we consider a redundant binary representation that makes additions of partial products fast, in order to accelerate a redundant binary multiplier which Booth's method is applied to. We evaluate delay time and circuit area of proposed redundant binary array multiplier. As a result, delay time and circuit area are reduced about 53% and 56%, respectively.