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A fast redundant binary multiplier excluding the intermediate sum operation of redundant binary adders

机译:快速冗余二进制乘法器,不包括冗余二进制加法器的中间和运算

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摘要

Accelerating methods that use a redundant binary representation for multipliers are good for VLSI implementation and have been concentrated lately. We examine an accelerating method for redundant binary multipliers using second order Booth's method. At a redundant binary multiplier which Booth's method is applied to, partial products are generated by every two digit of a multiplier and are accumulated. In this paper, we consider a redundant binary representation that makes additions of partial products fast, in order to accelerate a redundant binary multiplier which Booth's method is applied to. We evaluate delay time and circuit area of proposed redundant binary array multiplier. As a result, delay time and circuit area are reduced about 53% and 56%, respectively.
机译:将冗余二进制表示形式用于乘法器的加速方法非常适合VLSI实施,并且最近得到了集中。我们使用二阶布斯方法研究了冗余二进制乘法器的加速方法。在应用Booth方法的冗余二进制乘法器中,乘法器的每两位产生部分乘积并累加。在本文中,我们考虑了一种冗余二进制表示形式,该表示形式可以快速增加部分乘积,以加快应用Booth方法的冗余二进制乘数。我们评估了建议的冗余二进制阵列乘法器的延迟时间和电路面积。结果,延迟时间和电路面积分别减少了约53%和56%。

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