An advanced CMOS technology for low power and high performance LSIs in sub 100 nm CMOS

摘要

In an advanced CMOS LSI, not only high speed but also reduction of power dissipation is strongly required for performance enhancement of advanced systems. Moreover; in sub 100 nm CMOS technology, device design of MOSFET, such as gate insulator thickness and threshold voltage, severely affect to stand-by power dissipation owing to its gate leakage current and cut off current. In this paper, a design methodology of sub 100 nm CMOS is studied from power dissipation and performance enhancement points of views.