The layout architecture of flexible cells with continuously variable drive capabilities and its application to dynamic CMOS combinatorial logic circuits

摘要

In order to achieve a quick timing closure, we propose the layout architecture of flexible cells for dynamic CMOS combinatorial logic circuits by Domino and NORA with continuously variable transistor widths, based on the concept of FHM (Flexible Hardware Model) proposed by M. Imai et al. [1,2]. Taking AO23 (3-paralallel OR with 2-input AND) and full adder up as a typical combinatorial cell, we established the accurate models of delay time, power consumption and energy (= power consumption × delay time) with less than 3.4% average relative errors for the two flexible cells to three independent design measures of transistor width, interconnection RC, and fan-out capacitance, based on 0.35 μm design rule.