A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit

摘要

This paper presents a BiCMOS dynamic multiplier, which is free from race and charge sharing problems, using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit. Based on a 1 /spl mu/m BICMOS technology, a 1.5 V 8/spl times/8 multiplier designed, shows a 2.3/spl times/ improvement in speed as compared to the CMOS static one.