Three transistor multi-state dynamic memory cell for embedded CMOS logic applications

摘要

Methods are disclosed in making a multi-state dynamic memory using a three transistor cell. The cell construction is consistent with a logic semiconductor process and is therefore useful for embedded memory applications. Considerations are given to write levels, read levels, reference devices, and sense amplifier design. Two cell enhancements are proposed: substituting a PFET in place of and NFET for the write select transistor so that improved noise margin can be achieved and adding a capacitor for extended refresh times. Methods are also introduced to reduce select transistor leakage current during the deselected state.