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Potential Modeling of Oxide Engineered Doping-Less Dual-Material-Double-Gate Si-Ge MOSFET and Its Application

机译:氧化物工程掺杂较少双材料双栅Si-GE MOSFET的潜在建模及其应用

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This paper discusses and analyzes, doping-less dual-material-double-gate (DL-DMDG) silicon-germanium (Si-Ge) MOSFET using oxide engineering technique. In oxide engineering technique, the dual material gate oxide is used in such a way that the permittivity of oxide under the control gate is less than that of screening gate (epsilon(1) epsilon(2)). Such an arrangement enhances the electric field distribution in the channel region which increases the carrier velocity and hence, the trans-conductance. In this device charge plasma concept has been applied to an intrinsic Si-Ge substrate to induce n-type plasma. By using 2D-Poission equation analytical modeling of surface potential and electric field has been derived with respect to channel length and thickness. The analytical results have been validated with numerical device simulator. The result shows that the gate control over surface potential distribution increases by employing the oxide engineering techniques. Hence, SCEs are reduced. The electrostatic performance of proposed device has been compared with the double material gate oxide Si-Ge on insulator (DMGO-SGOI) MOSFET. Using device simulation, it has been obtained that the proposed device shows higher immunity to SCEs in comparison to DMGO-SGOI MOSFET. Further, source follower amplifier using NMOS transistor as current source has been designed using this device. Its drain current, trans-conductance, output voltage and gain have been investigated for different oxide materials. The DL-DMDG MOSFET incorporating oxide engineering technique offers higher amplification gain with the application of high permittivity oxide material at the screening gate.
机译:本文使用氧化物工程技术讨论和分析,掺杂较少的双材料双栅极(DL-DMDG)硅 - 锗(SI-GE)MOSFET。在氧化物工程技术中,双重材料栅极氧化物以这样的方式使用,使得控制栅极下方的氧化物介电常数小于筛分栅极(ε(1)εε(2))。这种布置增强了沟道区域中的电场分布,其增加了载流速,因此,传导率。在该装置中,电荷量概念已被施加到内在的Si-Ge衬底以诱导n型等离子体。通过使用2D-普遍的方程,对沟道长度和厚度来推导表面电位和电场的模拟。分析结果已通过数控模拟器验证。结果表明,通过采用氧化物工程技术来增加表面电位分布的栅极控制。因此,SCES减少。所提出的装置的静电性能与绝缘体(DMGO-SGOI)MOSFET上的双层材料型氧化物Si-Ge进行了比较。使用设备仿真,已经获得了与DMGO-SGOI MOSFET相比,所提出的装置对SC来表现出更高的免疫力。此外,使用NMOS晶体管作为电流源的源跟随放大器已经使用该装置设计。对不同的氧化物材料研究了其漏极电流,传导,输出电压和增益。包含氧化物工程技术的DL-DMDG MOSFET通过在筛选栅极中施加高介电常数氧化物材料提供更高的放大增益。

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