首页> 外国专利> HIGH-K CAPPED CUTOFF DIELECTRIC BAND GAP ENGINEERED SILICON-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR AND METAL-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR SUITABLE FOR NAND FLASH APPLICATIONS OF A 45NM NODE OR GREATER

HIGH-K CAPPED CUTOFF DIELECTRIC BAND GAP ENGINEERED SILICON-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR AND METAL-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR SUITABLE FOR NAND FLASH APPLICATIONS OF A 45NM NODE OR GREATER

机译:适用于45NM节点或更大的NAND闪存应用的高介电常数截止介电带隙工程化的氧化硅-氮化物-氧化物-半电子和金属氧化物-氮化物-氧化物-半电子

摘要

PURPOSE: A high-k capped cutoff dielectric band gap engineered silicon-oxide-nitride-oxide-semiconductor(SONOS) and a metal-oxide-nitride-oxide-semiconductor(MONOS) are provided to suppress gate injection by a high-k capping layer, thereby arranging a larger memory window and a lower elimination saturation level.;CONSTITUTION: A semiconductor body comprises a channel which includes a channel surface, and a drain(12) and source(11) arranged near the channel. A tunneling dielectric layer(13,14,15) is touched to the channel surface. A charge trapping dielectric layer(16) is placed on the tunneling dielectric layer. A cutoff dielectric layer(17A,17B) is placed on the charge trapping dielectric layer. A gate(18) is placed on the cutoff dielectric layer, charge trapping dielectric layer, and tunneling dielectric layer.;COPYRIGHT KIPO 2012
机译:用途:提供高k上限截止介电带隙工程氧化硅-氮化物-氧化物半导体(SONOS)和金属氧化物-氮化物-氧化物半导体(MONOS),以通过高k上限抑制栅极注入组成:半导体本体包括:沟道,其包括沟道表面;以及漏极(12)和源极(11),其设置在沟道附近。隧道介电层(13、14、15)接触沟道表面。将电荷俘获电介质层(16)放置在隧穿电介质层上。截止电介质层(17A,17B)放置在电荷俘获电介质层上。在截止电介质层,电荷俘获电介质层和隧穿电介质层上放置一个栅极(18)。;COPYRIGHT KIPO 2012

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