An FPGA Implementation of Low Dynamic Power & Area Optimized 32-Bit Reversible ALU

摘要

Today's Computer chips are facing a severe problem with power dissipation in addition to that heat generation. Reversible logic reduces power consumption as zero-energy computation has inspired it. It has various areas envisioned for its applications; they are low power CMOS design, Quantum & Optical computing, Nano-Technology, DSP, etc. Using this Reversible logic different combinational circuits are designed, like Decoders & Multiplexers. They have enhanced performance when compared to the conventional Circuits. This paper describes Design and Implementation of 32-Bit ALU built using reversible decoder controlled combinational circuits on Spartan3E (XC3S500E-FG320-5) FPGA. This proposed designed architecture provides 1.6 times less dynamic power consumption to conventional design and occupies 3% of the total memory in Spartan3E FPGA and saves area by 91% to the traditional design. This architecture has been modelled with Verilog in Xilinx ISE Design Suite 14.3.